GDS II is a database file format which is the de facto industry
standard for data exchange of integrated circuit or IC layout artwork.
It is a binary file format representing planar geometric shapes, text
labels, and other information about the layout in hierarchical form.
The data can be used to reconstruct all or part of the artwork to be
used in sharing layouts, transferring artwork between different tools,
or creating photo masks. Initially, GDS II was designed as a format
used to control integrated circuit photo mask plotting. Despite its
limited set of features and low data density, it became the industry
conventional format for transfer of IC layout data between design
tools of different vendors, all of which operated with proprietary
data formats. It was originally developed by Calma for its layout
design software, "Graphic Data System" ("GDS") and "GDS II". Now the
format is owned by Cadence Design Systems.
GDS II files are usually the final output product of the IC design
cycle and are given to IC foundries for IC fabrication. GDS II files
were originally placed on magnetic tapes. This moment was fittingly
called tape out though it is not the original root of the term.
Objects contained in a GDS II file are grouped by assigning numeric
attributes to them including "layer number", "datatype" or "texttype".
While these attributes were designed to correspond to the "layers of
material" used in manufacturing an integrated circuit, their meaning
rapidly became more abstract to reflect the way that the physical
layout is designed. As of October 2004, many EDA software vendors have
begun to support a new format, OASIS, which may replace GDS I
source:http://www.layouteditor.net/wiki/GDSII
Monday, December 17, 2012
Thursday, May 3, 2012
VEDA IIT Recruitment Test - 26th May 2012
'VEDA IIT Recruitment Test' is scheduled on 26th May 2012 . Apply online at www.vedaiit.com before 23rd May 2012
VEDA IIT Recruitment Test Details:
Exam Date : *Entrance Test will be conducted on 26th May 2012
Exam Time : 10:00 A.M
Exam Duration : 3 Hours
Last Date to Apply: DD for Rs.300/- should be drawn in favor of VEDA Institute of Information Technology Pvt. Ltd., Hyderabad should reach VEDA IIT by 23rd May 2012
How to Apply : Please visit www.vedaiit.com and click on 'Apply for Jobs'
Venue : VEDA IIT, Plot No. 90,
Annapurna Studios/ VEDA Lane,
Road No 2, Banjara Hills,
Hyderabad
Phone: + 91 40 3061 5555
or
JNTUH ,hyderabad kukatpalli.
Syllabus : 1. Digital Design & Micro Processors
2. C Programming
3. Aptitude
Saturday, March 3, 2012
Recruitment of Engineer Trainees in VLSI Design (Logic/Physical) and Embedded System Design at VEDAIIT for March 2012
Application for Recruitment of Engineer Trainees in VLSI Design (Logic/Physical) and Embedded System Design
please click here for more information and for apply online
http://www.vedaiit.com/applicationformrt.htm
DD for Rs.300/- should be drawn in favor of VEDA Institute of Information Technology Pvt. Ltd., Hyderabad should reach VEDA IIT by 15th Mar 2012
*Short listed candidates will be called for a written test
*Hall Tickets will be dispatched from 14th Mar 2012 on wards
*Entrance Test will be conducted on 17th Mar 2012
*DD's should be sent to the following address.
VEDA IIT, Road. No:2,
Annapurna Studio Lane
Banjara Hills, Hyderabad –34
*Write your Name, Program applying for, Registration Number, address and Contact Number on the reverse of DD.
for syllabus click here....
Monday, January 23, 2012
VLSI Terminology: Definition of process technology
Definition of: process technology
With regard to digital integrated circuits, process technology refers to the particular method used to make silicon chips. The driving force behind the manufacture of integrated circuits is miniaturization, and process technology boils down to the size of the finished transistor and other components. The smaller the transistors, the more transistors in the same area, the faster they switch, the less energy they require and the cooler the chip runs (given equal numbers of transistors).
Measured in Nanometers
The size of the features (the elements that make up the structures on a chip) used to be measured in micrometers. A 3 µm process technology, also called a "technology node" and "process node," referred to a silicon chip with features three micrometers in size. Today, features are measured in nanometers. A 45 nm process technology refers to features 45 nm or 0.45 µm in size.
Elements Measured
Historically, the process technology referred to the length of the silicon channel between the source and drain terminals in field effect transistors (see FET). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.
An Example of Progress
Consider that the process technology of the first 486 chip in 1989 was one micron (1,000 nanometers). By 2003, the state-of-the-art decreased to 90 nm ("90 nano"). In 15 years, feature sizes were reduced by slightly less than one millionth of a meter. What may seem like a minuscule, microscopic change to the casual observer took thousands of man years and billions of dollars worth of research and development. Note the huge variance in semiconductor feature sizes starting in the 1950s (see chart below).
Chips Are Nanotechnology
Intel introduced 45 nm processors in 2008. To understand how tiny 45 nanometers is, it would take two thousand 45 nm objects laid side-by-side to equal the thickness of one human hair.
In 2010, 32 nm chips were introduced, and feature sizes as low as 11 nm are expected in the future. For some time, chips have been in the realm of nanotechnology, which refers to elements 100 nanometers and smaller.
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