List of Verilog Simulators in Alphabetical Order by Name

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List of Verilog Simulators in Alphabetical Order by Name

Simulator Name	Author/Company	Languages	Description
Active-HDL/Riviera	Aldec	VHDL-2002, V2001, SV2005	A simulator with complete design environment aimed at FPGA-applications. Aldec licenses Active-HDL to FPGA-vendors, and the underlying engine can be found in the design-suites of those vendors. While ActiveHDL is a low-cost product, Aldec also offers a more expensive, higher-performance simulator called "Riviera."
Quartus II Simulator	Altera	VHDL-1993, V2001, SV2005	Altera's simulator bundled with the Quartus II design software. Supports Verilog, VHDL and AHDL.
Verilog-XL	Cadence	V1995	The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommends Incisive Enterprise Simulator for new design projects, as XL no longer receives active development. Nevertheless, XL continues to find use in companies with large codebases of legacy Verilog. Many early Verilog codebases will only simulate properly in Verilog-XL, due to variation in language implementation of other simulators.
Speedsim	Cadence Design Systems	V1995	Cycle based simulator originally developed at DEC. The DEC developers spun off to form Quickturn Design Systems. Quickturn was later acquired by Cadence, who discontinued the product in 2005. Speedsim featured an innovative slotted bit-slice architecture that supported simulation of up to 32 tests in parallel.
Incisive Enterprise Simulator('big 3')	Cadence Design Systems	VHDL-2002, V2001, SV2005	Cadence initially acquired Gateway Design, thereby acquiring Verilog-XL. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. The modern version of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog support. It also provides support for the e verification language, and a fast SystemC simulation kernel.
SMASH	Dolphin Integration	V1995, V2001, VHDL-1993	SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms.
Super-FinSim	Fintronic	V2001	This simulator is available on multi-platform, claiming IEEE 1364-2001 compliance.
PureSpeed	Frontline	V1995	The simulator had a cycle-based counterpart called 'pure cycle'. FrontLine was sold to Avant!, which was later acquired by Synopsys. Synopsys discontinued Purespeed in favor of its well-established VCS simulator.
ModelSim('big 3')	Mentor Graphics	VHDL-2002, V2001, SV2005	The original Modeltech (VHDL) simulator was the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. However, as the Verilog component of ModelSim is neither the fastest nor most fully featured simulator on the market, competition from Synopsys and Cadence, led to a continual decrease in ModelSim popularity.
SILOS	Simucad Design Automation	V2001	As one of the low-cost interpreted Verilog simulators, Silos III enjoyed great popularity in the 1990s. Simucad's most current version, Silos-X, is sold as part of a tool-suite.
Veritak	Sugawara Systems	V2001	It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution.
Verilogger Extreme,Verilogger Pro	SynaptiCAD	V2001,V1995	Verilogger Pro is a low-cost interpreted simulator based on Elliot Mednick's VeriWell code base. Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro.
VCS	Synopsys	VHDL-2002, V2001, SV2005	Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, VCS (Verilog Compiled code Simulator) was purchased by Synopsys, where development continued. Due to a strategic decision to support SystemVerilog (instead of SystemC), and the acquisition of Superlog (the forerunner to SystemVerilog), Synopsys/VCS was the first SystemVerilog simulator in the market.
CVC	Tachyon Design Automation	V2001, V2005	CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode.
Z01X	WinterLogic	V2001,SV2005	Developed as a fault simulator but can also be used as a logic simulator.
ISE Simulator	Xilinx	VHDL-93, V2001	Xilinx's simulator comes bundled with the ISE Design Suite. ISE Simulator (ISim) provides support for mixed-mode language simulation including, but not limited to, simulation of designs targeted for Xilinx's FPGAs and CPLDs.

Some commercial simulators (such as ModelSim) are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are offered free of charge.

Multi-core processor

Multi-core processor

From Wikipedia, the free encyclopedia

A multi-core processor is a single computing component with two or
more independent actual processors (called "cores"), which are the
units that read and execute program instructions. The data in the
instruction tells the processor what to do. The instructions are very
basic things like reading data from memory or sending data to the user
display, but they are processed so rapidly that human perception
experiences the results as the smooth operation of a program.
Manufacturers typically integrate the cores onto a single integrated
circuit die (known as a chip multiprocessor or CMP), or onto multiple
dies in a single chip package.

Processors were originally developed with only one core. A many-core
processor is a multi-core processor in which the number of cores is
large enough that traditional multi-processor techniques are no longer
efficient[citation needed] — largely because of issues with congestion
in supplying instructions and data to the many processors. The
many-core threshold is roughly in the range of several tens of cores;
above this threshold network on chip technology is advantageous.

A dual-core processor has two cores (e.g. AMD Phenom II X2, Intel Core
Duo), a quad-core processor contains four cores (e.g. AMD Phenom II
X4, the Intel 2010 core line that includes three levels of quad-core
processors, see i3, i5, and i7 at Intel Core), and a hexa-core
processor contains six cores (e.g. AMD Phenom II X6, Intel Core i7
Extreme Edition 980X). A multi-core processor implements
multiprocessing in a single physical package. Designers may couple
cores in a multi-core device tightly or loosely. For example, cores
may or may not share caches, and they may implement message passing or
shared memory inter-core communication methods. Common network
topologies to interconnect cores include bus, ring, two-dimensional
mesh, and crossbar. Homogeneous multi-core systems include only
identical cores, heterogeneous multi-core systems have cores which are
not identical. Just as with single-processor systems, cores in
multi-core systems may implement architectures such as superscalar,
VLIW, vector processing, SIMD, or multithreading.

Multi-core processors are widely used across many application domains
including general-purpose, embedded, network, digital signal
processing (DSP), andgraphics.

The improvement in performance gained by the use of a multi-core
processor depends very much on the software algorithms used and their
implementation. In particular, possible gains are limited by the
fraction of the software that can be parallelized to run on multiple
cores simultaneously; this effect is described by Amdahl's law. In the
best case, so-called embarrassingly parallel problems may realize
speedup factors near the number of cores, or even more if the problem
is split up enough to fit within each core's cache(s), avoiding use of
much slower main system memory. Most applications, however, are not
accelerated so much unless programmers invest a prohibitive amount of
effort in re-factoring the whole problem. The parallelization of
software is a significant ongoing topic of research.

VLSI FLOW ..

VLSI Design FLOW .. 

shown below...

FPGA Manufacturers

FPGA Manufacturers

The internet sources claim that there are at least five companies in the world that involved with the manufacturing and fabrication of FPGAs. These companies are:

1. Xilinx
2. Altera
3. Lattice
4. Actel
5. SiliconBlue

Among these companies Xilinx is the biggest name, as it invented the FPGAs in 1984 and may be deemed as global technology leader in the field of FPGAs.However, Altera is not a small name either. Statistics available on internet reflect that both Xilinx and Altera hold the major FPGA market share. As compared with the first two companies Lattice, Actel and SiliconBlue are small players.

Verilog vs VHDL:Salient Features of Languages

Salient Features of Languages

 

Some of the most widely compared and contrasted features of Verilog and VHDL are:

 

1.  Concurrency : A common characteristic of both these hardware description languages is that unlike software programming languages like C, Java and C++ etc., both these languages are concurrent in their behavior and program execution, as these languages are meant to design and simulate hardware.

2.     Predefined Constructs: As compared with VHDL, Verilog HDL has more predefined operators, predefined gates and predefined resolution functions. Verilog also includes don't care notation.

3.      Lower Level Modeling Capability: Verilog is better suited to modeling devices at lower level (i.e., Gate Level and Switch Level) than VHDL. This is why Verilog is deemed more efficient and appropriate for IC designing.

4.      Modeling Primitive Capability: As compared with VHDL, Verilog includes convenient truth table syntax to model primitives. However, the VITAL packages in VHDL provide this feature.

5.      High Level Modeling Capability: As compared with Verilog, VHDL includes more constructs (abstract data types and packages etc.) for high level modeling. This is why VHDL is considered appropriate for system level modeling.

6.      Case Sensitivity: Unlike VHDL, Verilog is a case sensitive language.

7.      Semantics: Both VHDL and Verilog have simulation-based semantics.

8.      Compilation and Interpretation: VHDL is compiled, while Verilog is an interpretative language.

9.      Simulation and Control Capabilities: Verilog defines a set of basic simulation control capabilities (system tasks) within language. As a result of these predefined system tasks and a lack of complex data types, Verilog users often run batch or command-line simulations and debug design problems by viewing waveforms from simulation results database. Unlike Verilog, VHDL does not define any simulation control and monitoring capabilities within language. These capabilities are tool-dependent. Due to the lack of language-defined simulation control command and because of user defined type capabilities, VHDL users usually rely on interactive GUI environments for debugging design problems.

10.  Dynamic Memory Allocation: VHDL supports dynamic memory allocation (pointer types), while Verilog has no such feature.

11.  Roots of Languages: VHDL is more readable and a strongly typed language with its roots from Ada. While, Verilog because of having its roots from C is more like C and is considered inherently sequential. Because of its affinity with C, Verilog is preferred by C programmers.

12.  Lack of Constructs: Not all the constructs and operators are included in both languages. For example, unlike Verilog, VHDL does not have unary reduction operator. Similarly, unlike VHDL, Verilog does not have mod operator and concurrent procedure statement. So neither of these two hardware description languages is perfect.

13.  Data types: Verilog has very simple data types, while VHDL allows users to create more complex data types.  

14.  Physical Types: VHDL supports physical types while Verilog does not support physical types.

15.  Named Events: Verilog supports named events while VHDL does not support named events.

16.  Enumerated Types: VHDLhas enumerated types (FSM modeling) while Verilog does not support this concept.  

17. Associative/Sparse arrays: Verilog does not support the concept of Associative/sparse arrays,while VHDL partially supports this concept,which can be modeled in VHDL using access types.

18. Associative/Sparse arrays: There is no concept of class/inheritance in both Verilog and VHDL. 

19. Data Packing: Both Verilog and VHDL do not support data packing.  

20. Conidtional & Iterative Generation: Both Verilog (using if,if-else,case and for) and VHDL (using if and for) support conditional and iterative genration.   

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Verilog vs VHDL:Superior Features of Verilog

Superior Features of  Verilog:

·         Verilog has clearer distinction between register and nets. Nets are used to model electrical connections, while registers hold values and act as memory elements.

·         Nets have strengths and delay properties which emphasize their physical aspects. The delay may consist of up to 9 values; a different value may be assigned for each transition 0, 1 or z and for each minimum, typical and maximum case. Such a delay attached to a net is added to the delay of each assigned statement. The net types include wire,tri,wand,triand,wor,trior,tri0,tril(resistive),supply0,supply1 and trireg (with charge storage).

·         Primitive gates include and, or, xor & not.

·         Verilog is concise and easier to learn as compared with VHDL. Unlike Verilog, VHDL is extremely verbose, which means it requires many characters to say something simple. This is why there are many different ways of saying the same thing in VHDL which makes it complicated and confusing. VHDL is exact in nature and difficult to learn. Verilog is deemed quicker to code and debug as compared with VHDL.

·         Unlike VHDL, Verilog has fork-join block. This construct lets you have nested parallel sequential blocks inside each other. This is a very powerful feature which is sometimes termed as 'multi-threading'. You cannot have this feature in VHDL unless you use explicit synchronizations between two different processes.

·         Unlike VHDL, Verilog is not a strongly typed language and this is why a 32-bit bus may be connected with and 8-bit bus by just padding the extra bits. Verilog does not require additional coding to convert from one data type to another data type like integer to bit-vector. So it does not have to pay the performance penalty caused by strong type checking and the designer productivity is also expected to be high in this case.

Verilog vs VHDL :Superior Features of VHDL

 Superior Features of  VHDL:

·        Unlike Verilog, the concept of packages in VHDL, library management and separate compilation makes it an ideal candidate for higher level system modeling. There is no concept of packages in Verilog. Functions and procedures used within a module have to be defined inside the same module and thus they cannot be shared by different modules. However, the concept of package in Verilog may be emulated by declaring and instantiating a fictitious module with functions and procedures. Verilog, unlike VHDL, does not support library management and separate compilation. This is why; Verilog requires all modules being used in same simulation must be written in the same file.

·         Unlike VHDL, Verilog types are very restrictive and are specific to IC modeling (wire, supply0, supply1 etc.). Many abstract data types may be defined in VHDL while Verilog data types are predefined.

·         Unlike VHDL, Verilog has no concept of configurations and it lacks generics and textio.

·         Unlike VHDL, Verilog has no access types.

·         Unlike Verilog, VHDL has extensive type checking feature; this is why many errors may be caught before synthesis and simulation.

·         VHDL provides more details in assignment and application of individual cells and signals within FPGA, but this requires a much better understanding of the FPGA. As compared with VHDL, Verilog despite being much easier to learn is neither efficient in use of available cells nor does it necessarily generate the fastest running implementation from the components available in FPGA.

·         Unlike Verilog, the verbosity of VHDL makes it self-documenting.

·         VHDL semantics are unambiguous and VHDL based design may easily be ported from one tool to another. This is why race conditions are never a concern for VHDL users. Simulation semantics in Verilog are more ambiguous than in VHDL. Though this ambiguity in Verilog semantics, gives designer more flexibility in applying optimization but it can also (and often does) result in race conditions if careful coding guidelines are not followed. It is highly probable that a Verilog based design generates different results on different vendors' tools or on different releases of the same vendor's tool.  

·         The advantage of strong typing in VHDL is that the potential bugs in the design may be identified as early in a verification process as possible. Many problems that strong typing uncover are identified during analysis/compilation of the source code.

Verilog vs VHDL

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different origins. Both of these languages hold major market shares of hardware description languages being used around the globe. It is difficult to say with certainty which one is better or superior; however, VHDL is older of the two. You can produce robust designs and comprehensive test environments with both languages, for both ASIC and FPGA.  

   

History and Origin of Languages

 

Both Verilog and VHDL have originated from different programming languages and are supported by different schools of thought. VHDL is based on Pascal and Ada, thus characteristics of both of these languages are reflected by VHDL. Verilog, unlike VHDL, is based on C programming language and is relatively new as compared with VHDL. Internet sources claim that Verilog is supported mostly by the HDL programmers with industrial experience and background while VHDL is supported mostly by academic circles.

The development of VHDL was initiated in 1981 by United States Department of Defense (DOD) to address the hardware life cycle crisis. VHDL was developed for US Department of Defense (DOD) to provide a consistent hardware modeling language for documentation of digital hardware designs. It was never meant to design actual hardware; its sole purpose was hardware modeling. Since Verilog HDL was an intellectual property of Gateway Design Automation, which was eventually acquired by Cadence, so to maintain the supposed competitive advantage and distance themselves from any strategic ties to Verilog HDL to avoid any potential competitive control from Cadence, the individual Electronic Design Automation (EDA) companies extended considerable influence, resources and dollars to turn this language into a hardware design language. These same individual EDA companies developed and implemented their own semi-unique versions of the language at different stages of its development and implementation. The reason that these EDA companies did not adopt Verilog HDL is that they all have a basic philosophy which states that they must own all of their core technology which was being violated in case of Verilog as it, being intellectual property of Cadence, was not open to public domain. Besides this the EDA vendors wanted to break Cadence's stranglehold on the software design tool and IC design market by pushing and promoting VHDL, which was an open language. VHDL became IEEE standard 1076 in 1987.VHDL was updated in 1993 and is known today as "IEEE standard 1076 1993".As an IEEE standard, VHDL must undergo a review process every five years or sooner to ensure its ongoing relevance to industry. The first such revision was completed in September 1993.

Unlike VHDL, Verilog has originated from the commercial and industrial world. It was developed as a part of a complete simulation system, which may be utilized for describing digital hardware systems as well. Verilog HDL was launched by Gateway in 1983.Gateway was bought by Cadence in 1989.Cadence had recognized that if Verilog HDL remained a closed language as compared with VHDL the pressures of standardizations would force the industry to VHDL. So Cadence opened Verilog to the public domain in 1991 by officially publishing it. Verilog HDL became IEEE standard in 1995.

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