Install gdata google python module in Ubuntu

python-gdata deb

After a long time am publishing the new post…

Am started a new mini project which upload a photo to picassa.google.com using python code. Am searching python API on the internet. I found a code. But when i run the code it shows error like 'did not find "gdata" module'. So am searching how to install python-gdata module in ubuntu. After my searching these term i found the solution simply…

First of all what is python-gdata?
python-gdata – Google Data Python client library

Distribution: Ubuntu 12.04.2 LTS

Repository: Ubuntu Universe i386

Package name: python-gdata

Package version: 2.0.14-2

Package architecture: all

Package type: deb

Binary package: python-gdata_2.0.14-2_all.deb

Source package: python-gdata

Installed size: 2,93 MB

Download size: 447,12 KB
The GData (Google data) APIs provide a simple protocol for reading and writing data on the web.
Each of the following Google services provides a Google data API:
* Base
* Blogger
* Calendar
* Code Search
* Contacts
* Document List
* Google Apps Provisioning
* Notebook
* Picasa Web Albums
* Spreadsheets
* YouTube
The Google data Python client library provides a library and source
code that make it easy to access data through Google data APIs.

Install how to???

1. First we need to update the linux index, so that run the following code first:

# sudo apt-get update

When i run the above code it will update the repositories and index.
2. Install python-gdata deb package by simply running these code:

# sudo apt-get install python-gdata

This command will download the python-gdata module succesfully.

VLSI : What is finfet?

FinFET

FinFET, also known as Fin Field Effect Transistor, is a type of non-planar or "3D" transistor used in the design of modern processors. As in earlier, planar designs, it is built on an SOI (silicon on insulator) substrate. However, FinFET designs also use a conducting channel that rises above the level of the insulator, creating a thin silicon structure, shaped like a fin, which is called a gate electrode. This fin-shaped electrode allows multiple gates to operate on a single transistor.

This type of multi-gate process extends Moore's law, allowing semiconductor manufacturers to create CPUs and memory modules that are smaller, perform faster, and consume less energy. Intel began releasing FinFET CPU technology in 2012 with its 22-nm Ivy Bridge processors.

source: http://www.computerhope.com/jargon/f/finfet.htm

Physical Design Flow I:Netlist In & Floorplanning

Netlist In
The first stage in physical design flow is reading in the netlist and the constraints to your tool of choice. Let us see what kinds of files we are dealing with here. I have used both Cadence and Synopsys tools extensively, so those are what I will base my examples on. However, every tool uses pretty much the same flow and even the same format files.

1. Gate Level Netlist
   Once you choose a process and a library, a synthesis tool will translate your RTL into a collection of interconnected logic gates that define the logic. The most common format is verilog. I had seen some VHDL and EDIF designs when I started my career, but I have only really worked with Verilog files.
2. Standard Cell Library
   In digital design, you have a ready made standard cell library which will be used for synthesis and subsequent layouts. Your netlist will have instantiation of these cells. For digital layout, you need layout and timing abstracts for these cells.
   • Layout Model – An abstract model of the standard cell layout is used instead of the complete layout. This will have PINs defined, so as to facilitate automatic routing by the tool as per your netlist. Synopsys tool ICCompiler use “FRAM” views as a PnR abstract. FRAM view is a cell view that has only the PINs and metal and via blockages defined. This makes sure that the interconnection between the PINs can be routed automatically and that the routing tool will not route over existing metal/via areas thus ruling out any shorts. Cadence EDI tools use LEF views, which again has only the PINs and Obstructions (blockages) defined. LEF is an ascii file, so go ahead and have a read.
   • Timing Model – Tools also need a timing model in the form of a .lib file. ICC takes a .db file, which is generated from a .lib. This liberty format file will have timing numbers for the various arcs in a cell, generally in a look up model. Please note that .libs may also have cell power information.
3. Technology File
   The rules pertaining to the process you have selected should also be given to the PnR tool. This includes metal widths, spacing, via definitions etc. ICC takes a milkyway techfile format, while EDI tools take a technology LEF file.
4. Timing Constraints
   SDC files define the timing constraints of your design. You will have the clock definitions, false paths, any input and output delay constraints etc.

These inputs once read in, will get you started with your database.

VEDA IIT: Recruitment test 2015: Trainee in all specializations of VLSI(LD/PD/AD/CL)

All India Recruitment test for Engineer Trainee in all specializations of VLSI(LD/PD/AD/CL), Embedded System Design and User Experience(UX) are announced.
Apply by June 01, 2015 (on line at www.vedaiit.org)
Recruitment test on June 06, 2015

application: 

http://vedaiit.org/application/VedaIITAutomation_2/codevalidate.php

http://vedaiit.org/#course_module