The main steps in the flow are:
Design Netlist (after synthesis)
Floor Planning
Partitioning
Placement
Clock-tree Synthesis (CTS)
Routing
Physical Verification
GDS II Generation
These steps are just the basic. There are detailed PD Flows that are used depending on the Tools used and the methodology/technology. Some of the tools/software used in the back-end design are :
Cadence (SOC Encounter, VoltageStorm, NanoRoute)
Synopsys (Design Compiler)
Magma (BlastFusion, etc)
Mentor Graphics (Olympus SoC, IC-Station, Calibre)
A more detailed Physical Design Flow is shown below. Here you can see the exact steps and the tools used in each step outlined.
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