Physical Design Flow I:Netlist In & Floorplanning

Netlist In
The first stage in physical design flow is reading in the netlist and the constraints to your tool of choice. Let us see what kinds of files we are dealing with here. I have used both Cadence and Synopsys tools extensively, so those are what I will base my examples on. However, every tool uses pretty much the same flow and even the same format files.

1. Gate Level Netlist
   Once you choose a process and a library, a synthesis tool will translate your RTL into a collection of interconnected logic gates that define the logic. The most common format is verilog. I had seen some VHDL and EDIF designs when I started my career, but I have only really worked with Verilog files.
2. Standard Cell Library
   In digital design, you have a ready made standard cell library which will be used for synthesis and subsequent layouts. Your netlist will have instantiation of these cells. For digital layout, you need layout and timing abstracts for these cells.
   • Layout Model – An abstract model of the standard cell layout is used instead of the complete layout. This will have PINs defined, so as to facilitate automatic routing by the tool as per your netlist. Synopsys tool ICCompiler use “FRAM” views as a PnR abstract. FRAM view is a cell view that has only the PINs and metal and via blockages defined. This makes sure that the interconnection between the PINs can be routed automatically and that the routing tool will not route over existing metal/via areas thus ruling out any shorts. Cadence EDI tools use LEF views, which again has only the PINs and Obstructions (blockages) defined. LEF is an ascii file, so go ahead and have a read.
   • Timing Model – Tools also need a timing model in the form of a .lib file. ICC takes a .db file, which is generated from a .lib. This liberty format file will have timing numbers for the various arcs in a cell, generally in a look up model. Please note that .libs may also have cell power information.
3. Technology File
   The rules pertaining to the process you have selected should also be given to the PnR tool. This includes metal widths, spacing, via definitions etc. ICC takes a milkyway techfile format, while EDI tools take a technology LEF file.
4. Timing Constraints
   SDC files define the timing constraints of your design. You will have the clock definitions, false paths, any input and output delay constraints etc.

These inputs once read in, will get you started with your database.